Starting current transient of the most flaming fro

2022-08-01
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Starting current transient of leading edge triggered PFC controller

leading edge triggered PFC converter controller brings many benefits to customers. The most important thing is that the control chip can operate in a unique way, that is, while the PFC converter provides current for the output capacitor, the next converter will obtain current from the same capacitor. This operation mode greatly reduces the current of R in the PFC output capacitor used to produce the next generation USB type-C connector MS during operation

The switching action of the front triggered topology is as follows: when the ramp voltage of the clock crosses the voltage at the output of the current error amplifier, the PFC switch will be turned on

the system has an initial condition problem. When the chip is powered first, the voltage at the output of the current error amplifier is clamped to ground like the input. In addition, because the feedback structure is specially designed for the cost division amplifier with reduced product, the output has limited dv/dt function. This results in a large current transient when the converter is initially powered on

depending on the initial precharge state of the output capacitor and the initial input voltage conditions, this will result in an overvoltage condition at the output

the solution to this problem is to add a clamping circuit to control the initial peak current limit, so that it is much lower than the design peak current limit. This clamp will be released quickly and allow the current peak limit to increase, but by then the current will have a long stroke and two test space difference amplifiers will be responsible for the control function

the attached circuit (Figure 1) shows the solution to this problem. This figure is about the circuit slus419 on page 13 of UCC38500 product manual

the resistance R29 from VREF to pklimit is divided into r29a and r29b. The sum of the two resistance values is the original resistance value before decomposition, that is, the resistance connected with VREF is 1/3 of the original resistance value, and the resistance connected with pklimit is 2/3 of the original resistance value. The emitter of the added PNP signal transistor (Q100) is connected to the intersection of the two resistors, and the collector of the transistor is connected to ground. The base of the transistor is connected to the intersection of the added resistor (R100) and the capacitor (C100). The other side of the added capacitor is grounded and the other side of the resistor is connected to VREF. The ratio between r12a and r12b determines that the transistor is off when the capacitor is fully filled

when the controller is powered first, the voltage at both ends of the added capacitor C100 is 0, and the transistor is kept on, so that the voltage at the intersection of r29a and r29b is close to the ground voltage. This reduces the peak current limit generated by the converter. Since the oil delivery volume of the oil delivery valve can be adjusted for loading, the voltage at both ends of the capacitor (C100) will increase with the increase of the charging current flowing through R100, so the voltage at the intersection of r29a and r29b will also increase, allowing the peak current to increase (this is the case until the effect of the added circuit is eliminated and the peak current limit conforms to the initial design). C100 and R100 shall be selected according to the following principle: the time constant shall be less than the value of any soft start circuit on PFC or downlink converter

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